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We strongly support your embedded development of JESD 204B converter.
This page provides a report we evaluated on the ADI device evaluation board.
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JESD 204B seminar schedule in 2018
Latest information
| I will introduce Analog Devices' IP core. Please check JESD204 Interface Framework LINK.Information is available here. AD-IP-JESD204:ADI-IP-JESD204 is an interface framework compatible with JEDEC JESD204B specification. Key Features and Benefits Design based on JEDEC JESD204B specification. 1 to 256 octets per frame, corresponding to 1 to 32 frames per multiframe. Up to 32 lanes can be set. Supports 12.5 Gbps line rate conforming to JESD 204 B specification. Supports 16.1 Gbps line rate not compliant with JESD 204 B specification. Equipped with functions of physical layer and data link layer. Equipped with AXI-Stream interface for data. Equipped with AXI 4-Lite interface for setting. Provided in RTL format.Available in Verilog-HDL Please get details from WIKI. |  |
| GF-Design GF180320 Implementation of AD-IP-JESD204B I implemented a receiver IP. Please refer to the resource. Evaluation experiment 1, ZCU 102 and FMCDAQ 2. Fit to the image. 2, Write the bit file. AD_FMC_DAQ2_TOP_DAC.bit 3, Check the waveform with the tip scope. 10 MHZ Output from DAC. Our sample design is original. In order to use the FPGA design, Xilinx Vivado 2017.2 is required. Download micro USB cable is required. (It is attached to ZCU 102)  | Block diagram when ADI-IP-JESD 204 is incorporated in Zynq Ultrascale + MPSoC |
| GF-Design GF180220 Implementation of AD-IP-JESD204B I implemented a receiver IP. Please refer to the resource. Evaluation experiment 1, ZCU 102 and FMCDAQ 2. Fit to the image. 2, Write the bit file. ADI_IP_RX_test.bit 3, Check the waveform with the tip scope. 10 MHZ input to ADC Our sample design is original. In order to use the FPGA design, Xilinx Vivado 2017.2 is required. Download micro USB cable is required. (It is attached to ZCU 102)  | Block diagram when ADI-IP-JESD 204 is incorporated in Zynq Ultrascale + MPSoC  |
Evaluation board operation confirmation list
| GFdesign | Evaluation image | JESD204B Converter | Evalution Board | Evalution Board | Design Reference Design |
| GF180320 |  | AD9144 Quad, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter | AD-FMCDAQ2 AD9680 dual, 14-bit, 1.0 GSPS, JESD204B ADC, the AD9144 quad, 16-bit, 2.8 GSPS, JESD204B DAC, | EK-U1-ZCU102-G Zynq UltraScale XCZU9EG-2FFVB1156 FPGA | Analog Devices IP Design GF180320-ROM.zip SAMPLE:AD_FMC_DAQ2_TOP_DAC.bit  |
| GF180220 |  | AD9680 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter | AD-FMCDAQ2 AD9680 dual, 14-bit, 1.0 GSPS, JESD204B ADC, the AD9144 quad, 16-bit, 2.8 GSPS, JESD204B DAC, | EK-U1-ZCU102-G Zynq UltraScale XCZU9EG-2FFVB1156 FPGA | Analog Devices IP Design  |
| GF180119 |  | AD9680 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter | AD-FMCDAQ2 AD9680 dual, 14-bit, 1.0 GSPS, JESD204B ADC, the AD9144 quad, 16-bit, 2.8 GSPS, JESD204B DAC, | EK-U1-ZCU102-G Zynq UltraScale XCZU9EG-2FFVB1156 FPGA | XILINX JESD204B IP design  |
| GF171220 |  | AD9172 Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers | EVAL-AD9172 12.6 GSPS RF DAC JESD204B high speed serial interface | EVAL-ADS7-V2EBZ Virtex-7 XC7VX330T-3FFG1157E FPGA | XILINX JESD204B IP design MATLAB  |
| GF171120 |  | AD9208 14-Bit, 3 GSPS, JESD204B, Dual Analog-to-Digital Converter | AD9208-3000 3GBPS JESD204B high speed serial interface | EVAL-ADS7-V2EBZ Virtex-7 XC7VX330T-3FFG1157E FPGA | MWE2017 60GHZ BASEBAND XILINX JESD204B IP design  |
| GF170818 |  | AD9164 16-Bit, 12 GSPS, RF DAC and Direct Digital Synthesizer | EVAL-AD9164 12 GSPS JESD204B high speed serial interface | EK-U1-KCU105-G XCKU040-2FFVA1156E FPGA | XILINX JESD204B IP design  |
| GF170619 |  | AD9625 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter | GF85XX-ADDA AD9625/AD9164 2.5 GSPS utilizing JESD204B high speed serial interface | DK-DEV-10AX115S-A 10AX115S2F45I1SG2 | ALTERA JESD 204 B IP design  |
GF170519 |  | AD9625 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter | AD-FMCADC2-EBZ 2.5 GSPS utilizing JESD204B high speed serial interface | DK-DEV-5ASTD5NES 5ASTFD5K3F40I3NES (SoC) | ALTERA JESD 204 B IP design  |
| GF170321 |  | AD9680 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter | AD-FMCDAQ2 AD9680 dual, 14-bit, 1.0 GSPS, JESD204B ADC, the AD9144 quad, 16-bit, 2.8 GSPS, JESD204B DAC, | ACADEMINO-PRO XC7A200T-3FBG484C | JESD204B Multiframe and ILAS Measure output timing  |
| GF161220 |  | AD9164 16-Bit, 12 GSPS, RF DAC and Direct Digital Synthesizer | EVAL-AD9164 12 GSPS JESD204B high speed serial interface | EVAL-ADS7-V2EBZ Virtex-7 XC7VX330T-3FFG1157E FPGA | XILINX JESD204B IP design  |
| GF161120 |  | AD9144 Quad, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter | AD-FMCDAQ2 AD9680 dual, 14-bit, 1.0 GSPS, JESD204B ADC, the AD9144 quad, 16-bit, 2.8 GSPS, JESD204B DAC, | ACADEMINO-PRO XC7A200T-3FBG484C JESD204B STARTUP KIT | XILINX JESD204B IP design MATLAB LTE TOOLBOX  |