JESD204b development
Gigafirm is an Alliance member company of Analog Devices.
We strongly support your embedded development of JESD 204B converter.
This page provides a report we evaluated on the ADI device evaluation board.
For questions about info@gigafimr.com
JESD 204B seminar schedule in 2018
Please look at the event link.
2018.4.19 JESD 204 B Technology Seminar 2018 - 1st (FREE) ...... Under planning
Latest information
I will introduce Analog Devices' IP core.
Please check JESD204 Interface Framework LINK.Information is available here.
AD-IP-JESD204:ADI-IP-JESD204 is an interface framework compatible with JEDEC JESD204B specification.
Key Features and Benefits
Design based on JEDEC JESD204B specification.
1 to 256 octets per frame, corresponding to 1 to 32 frames per multiframe.
Up to 32 lanes can be set.
Supports 12.5 Gbps line rate conforming to JESD 204 B specification.
Supports 16.1 Gbps line rate not compliant with JESD 204 B specification.
Equipped with functions of physical layer and data link layer.
Equipped with AXI-Stream interface for data.
Equipped with AXI 4-Lite interface for setting.
Provided in RTL format.Available in Verilog-HDL
Please get details from WIKI.
GF-Design GF180320
Implementation of AD-IP-JESD204B
I implemented a receiver IP. Please refer to the resource.
Evaluation experiment
1, ZCU 102 and FMCDAQ 2. Fit to the image.
2, Write the bit file. AD_FMC_DAQ2_TOP_DAC.bit
3, Check the waveform with the tip scope. 10 MHZ Output from DAC.
Our sample design is original.
In order to use the FPGA design, Xilinx Vivado 2017.2 is required.
Download micro USB cable is required. (It is attached to ZCU 102)
Block diagram when ADI-IP-JESD 204 is incorporated in Zynq Ultrascale + MPSoC
GF-Design GF180220
Implementation of AD-IP-JESD204B
I implemented a receiver IP. Please refer to the resource.
Evaluation experiment
1, ZCU 102 and FMCDAQ 2. Fit to the image.
2, Write the bit file. ADI_IP_RX_test.bit
3, Check the waveform with the tip scope. 10 MHZ input to ADC
Our sample design is original.
In order to use the FPGA design, Xilinx Vivado 2017.2 is required.
Download micro USB cable is required. (It is attached to ZCU 102)
Block diagram when ADI-IP-JESD 204 is incorporated in Zynq Ultrascale + MPSoC
Evaluation board operation confirmation list
GFdesign
GF180320
GF180220
GF180119
GF171220
GF171120
GF170818
GF170619
GF170519
GF170321
GF161220
GF161120
Evaluation image
JESD204B Converter
AD9144
Quad, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter
AD9680
14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter
AD9680
14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter
AD9172
Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
AD9208
14-Bit, 3 GSPS, JESD204B, Dual Analog-to-Digital Converter
AD9164
16-Bit, 12 GSPS, RF DAC and Direct Digital Synthesizer
AD9625
12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter
AD9625
12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3 V/2.5 V Analog-to-Digital Converter
AD9680
14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter
AD9164
16-Bit, 12 GSPS, RF DAC and Direct Digital Synthesizer
AD9144
Quad, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter
Evalution Board
AD-FMCDAQ2
AD9680 dual, 14-bit, 1.0 GSPS, JESD204B ADC, the AD9144 quad, 16-bit, 2.8 GSPS, JESD204B DAC,
AD-FMCDAQ2
AD9680 dual, 14-bit, 1.0 GSPS, JESD204B ADC, the AD9144 quad, 16-bit, 2.8 GSPS, JESD204B DAC,
AD-FMCDAQ2
AD9680 dual, 14-bit, 1.0 GSPS, JESD204B ADC, the AD9144 quad, 16-bit, 2.8 GSPS, JESD204B DAC,
EVAL-AD9172
12.6 GSPS
RF DAC
JESD204B high speed serial interface
AD9208-3000
3GBPS
JESD204B high speed serial interface
EVAL-AD9164
12 GSPS
JESD204B high speed serial interface
GF85XX-ADDA
AD9625/AD9164
2.5 GSPS utilizing JESD204B high speed serial interface
AD-FMCADC2-EBZ
2.5 GSPS utilizing JESD204B high speed serial interface
AD-FMCDAQ2
AD9680 dual, 14-bit, 1.0 GSPS, JESD204B ADC, the AD9144 quad, 16-bit, 2.8 GSPS, JESD204B DAC,
EVAL-AD9164
12 GSPS
JESD204B high speed serial interface
AD-FMCDAQ2
AD9680 dual, 14-bit, 1.0 GSPS, JESD204B ADC, the AD9144 quad, 16-bit, 2.8 GSPS, JESD204B DAC,
Evalution Board
EK-U1-ZCU102-G
Zynq UltraScale XCZU9EG-2FFVB1156 FPGA
EK-U1-ZCU102-G
Zynq UltraScale XCZU9EG-2FFVB1156 FPGA
EK-U1-ZCU102-G
Zynq UltraScale XCZU9EG-2FFVB1156 FPGA
EVAL-ADS7-V2EBZ
Virtex-7 XC7VX330T-3FFG1157E FPGA
EVAL-ADS7-V2EBZ
Virtex-7 XC7VX330T-3FFG1157E FPGA
EK-U1-KCU105-G
XCKU040-2FFVA1156E FPGA
DK-DEV-10AX115S-A
10AX115S2F45I1SG2
DK-DEV-5ASTD5NES
5ASTFD5K3F40I3NES (SoC)
ACADEMINO-PRO
XC7A200T-3FBG484C
EVAL-ADS7-V2EBZ
Virtex-7 XC7VX330T-3FFG1157E FPGA
ACADEMINO-PRO
XC7A200T-3FBG484C
JESD204B
STARTUP KIT
Design Reference Design
Analog Devices IP Design
GF180320-ROM.zip
SAMPLE:AD_FMC_DAQ2_TOP_DAC.bit
Analog Devices IP Design
XILINX JESD204B IP design
XILINX JESD204B IP design
MATLAB
MWE2017 60GHZ BASEBAND
XILINX JESD204B IP design
XILINX JESD204B IP design
ALTERA JESD 204 B IP design
ALTERA JESD 204 B IP design
JESD204B Multiframe and ILAS Measure output timing
XILINX JESD204B IP design
XILINX JESD204B IP design
MATLAB LTE TOOLBOX
